Continuous advancements in the field of very large scale integrated circuits (VLSIs) and very high speed integrated circuits (VHSICs) have resulted in smaller device geometries and millions of closely spaced interconnections in one or more levels that connect the various components on the chip. Due to continued market demands for higher speed and higher density microchips, there is a widely shared conviction that the minimum structure size of mainstream CMOS devices, which is currently at about 0.4 .mu.m corresponding to the 16-Mbit dynamic random access memory (DRAM) generation, will be scaled down to about 0.07 .mu.m. The intense research and development (R&D) effort directed towards DRAMs, for example, has rapidly increased memory chip capacity by six orders (1-Kbit to 1-Gbit) over the last 25 years. Technologies allowing a higher density of devices were the driving force in quadrupling the memory capacity of each generation. Recently, however, R&D for 256-Mbit and 1-Gbit chips has not succeeded in continuing to sufficiently increase the density, i.e. scale down the feature size in order to keep the chip size small enough, to allow economical production with available wafer sizes.
Among the many problems to be solved in order to achieve this aggressive scaling rule is the coupling (interference) noise between the interconnections (data links) in single as well as multilevel configurations. Coupling noise is very sensitive to scaling and is considered a main obstacle to achieving reliable high speed and high density microchips. Semiconductor memories are one of the devices in which data access speed and reliable operation are dominantly determined by the degree of coupling noise. This is due to the closely spaced data lines in a memory cell array area. Also, among semiconductor memories, DRAMs are most sensitive to the adverse effect of coupling noise. Experimental 1-Gbit DRAMs have been reported with substantial scaling down schemes of memory cell arrays. As the integration density of the DRAM has increased, new types of memory cell array noise have emerged as seemingly inevitable problems. Among them is inter- and intra-bit line (BL) coupling noise due to the BL to BL coupling capacitances, which are increased as the BL pitch (separation between BLs) becomes smaller. Inter-BL coupling noise originates from capacitive coupling of signals in adjacent BL pairs. Intra-BL coupling noise is due to coupling between the two BLs which form a BL pair, i.e. true and compliment BL.
Scaling down of DRAM calls for characterization and containment of various external and internal noise sources with respect to the small amount of signal charge. Well-known bit line noises such as those from bit line to word line and substrate coupling are insensitive to scaling and can be suppressed to a low level by employing a folded bit line structure. However, in 16-Mbit DRAMs and beyond, a new kind of noise due to bit line coupling becomes important because of an increase in inter- and intra-BL capacitance.
A few studies for analyzing BL capacitance using three-dimensional simulation in scaled DRAM cell arrays report that inter-BL capacitance accounts for more than 10 percent of the total BL capacitance in 64-Mbit DRAMs. The simulated ratio of the polycide BL's coupling capacitance C.sub.c) to the total BL capacitance C.sub.b) as a function of BL pitch is shown in graph 100 of FIG. 1. Different BL layer thicknesses are used to simulate the exact C.sub.c /C.sub.b ratio for each DRAM generation. For example, BL thickness of 0.18 and 0.14 .mu.m are used for the BL pitch of 0.6 and 0.28 .mu.m, respectively. C.sub.o is the substrate capacitance of the BL. Commercial software for interconnect parameter extraction was used for this simulation. As shown in FIG. 1, C.sub.c exceeds 30 percent of C.sub.b in 1-Gbit DRAM generation.
The inter- and intra-BL coupling noise may be minimized by proper scaling of the physical dimensions, especially thickness and width of the BL. But these schemes are limited by problems such as electromigration and the performance degradation due to the increase of the BL resistance at higher densities even with the advent of copper based interconnections.
To overcome the inter-BL coupling noise problems, a Twisted Bit Line (TBL) technique has been proposed and utilized in some DRAM chips. However, this
technique has two main problems: 1) an inability to suppress the intra-BL pair coupling noise, and 2) the need for additional chip area for twisting the BLs (at least four twisting areas per divided memory array) and for four dummy cells per BL pair. It thus seems that this TBL technique will not reduce the chip area sufficiently in scaled-down memory arrays to realize economic mass production of Gbit level DRAMs.
To illustrate, FIG. 2(a) shows an example of the BL configuration in the conventional TBL technique. In the conventional TBL scheme, the BLs are equally divided into four sections (or possible twisting points) A, B, C and D. A BL pair 210 is twisted at the points `B` and `D`, and the adjacent pair 212 is twisted at the points `A` and `C`. This basic unit of two BL pairs is repeated over the entire memory cell array. In FIG. 2(a), the two pairs' structure is repeated once in pairs 214 and 216. WLs 218 intersect with the BLs at cells 220 such that WL 0 intersects with the true BLs (0, 1, 2, and 3) and WL 1 intersects with the complimentary BLs (0, 1, 2, and 3). As a result of BL twisting in this manner, the inter-BL pair coupling capacitances for adjacent and compliment BLs (BL and BL) are equal for both the upper and lower sides of any BL pair. Therefore, the inter-BL pair noise cancels out, but the intra-BL pair noise still remains the same. Since the intra-BL pair noise is more detrimental than the inter-BL pair noise, in readout or sensing operations, more serious problems can be expected in applying the conventional TBL schemes to the development of the higher density DRAMs, such as 1-Gbit DRAMs and beyond. For example, the signal loss in a 1-Gbit level BL structure, where the ratio of the coupling capacitance to the total BL capacitance is 35 percent, is estimated to be more than 30 percent of the total signal amplitude, in spite of the use of the conventional TBL schemes.
In addition, the conventional TBL schemes have disadvantages with regard to chip lay-out density. The conventional TBL schemes require additional chip area for twisting BLs and also for the four dummy cells per BL pair. It is estimated that a 6.5 percent chip area increase will occur when implementing the conventional TBL schemes in a 1-Gbit DRAM. As a result, more effective techniques to reduce the BL coupling noise without incurring those penalties are necessary to realize 1-Gbit DRAMs and beyond.
U.S. Pat. No. 5,534,732 ("DeBrosse et al.") discloses a multiple twisted BL (MTBL) technique intended to address the inherent problems of the conventional TBL technique. FIG. 2(b) shows one the possible examples of this DeBrosse et al. scheme. DeBrosse et al. teaches an interconnection array layout and twist method which balances inter-pair coupling and eliminates intra-pair coupling by utilizing a single twist region 230 separating two regions 232 and 234 in which the BLs run parallel to each other. In region 232, complimentary line conductors are displaced two pitches down from corresponding true line conductors. In region 234, complimentary line conductors are displaced two pitches up from corresponding true line conductors. Each pairing of line conductors is separated by a line conductor which is different in each of the two regions 232 and 234.
In this twisting scheme, four BLs 236 are twisted once such that no true BL (BL) is immediately adjacent to its associated compliment BL (BL) in both the memory arrays of before and after twisting. In addition, each BL is located and twisted such that for any given BL, capacitive coupling occurring between a given BL and immediately adjacent true BLs is balanced by capacitive coupling occurring between a given BL and immediately adjacent compliment BLs associated with the same immediately adjacent true BLs. This pattern is repeated for the length of the array as illustrated by BL group 238 and 240. As a result, the Debrosse et al. MTBL scheme eliminates both the inter- and intra-BL pair coupling noise completely. It imposes, however, serious problems in memory cell arrangement, chip area increase and BL pair capacitive and resistive imbalance. Special process and design technologies (e.g., special memory cell type, layout technique and sense amplifier design) will be necessary to implement this multiple twisted BL scheme.
Another problem of the application of the twisted scheme disclosed in DeBrosse et al. is its limitation to a specific arrangement of memory cells. This scheme cannot be applied to the folded-BL memory cell arrangement that has been adopted by most manufacturers of memory devices over the past twenty years. Proper read/write operation cannot be achieved with the folded-BL arrangement because both BLs in a BL pair (true and complement) access memory cells 242 for the same word line 244. The other problem of this twisted scheme is the requirement of dummy BLs (not shown) in both the "top" and "bottom" edges of the memory array to balance respective BL capacitances. These dummy BLs will increase the chip area considerably in addition to the BL twisting area. In addition, due to the non-symmetrical BL twisting patterns, the capacitive imbalance within BL pairs will be a serious problem for proper operation. To overcome the capacitive imbalance, this scheme will require either a special sense amplifier or a special BL layout which will consume extra chip area.
In scaled high-density DRAMs with main word line driver schemes, two characteristics of the devices create word line coupling noise which is as serious a problem as the bit line coupling noise. One characteristic is that the bootstrapped word line voltage (V.sub.WL) has to be higher than the power supply voltage (V.sub.cc) to compensate for the threshold voltage drop across the cell transistor. The other characteristic is the use of a metal line as a second word line to reduce the word line's RC-delay. For DRAMs with main/sub word line driver schemes, the same situation applies because, in this case, the word line control lines are metal layers with almost the same line pitch. As a result, taking account of the scaling down of the cell transistor's threshold voltage, along with the V.sub.cc scaling down, the word line coupling noise can be an even more serious problem than the bit line coupling noise and should be minimized in scaled high-density DRAMs.
FIG. 6 shows one of the worst case data patterns for word line coupling noise. FIG. 6(a) shows a BL pair 602 intersecting with four WLs (i, j, k and 1) before connecting to a sense amplifier 604. In the first active cycle, shown in FIG. 6(b), memory cell j having data `0` is selected and, simultaneously, word line k, which is adjacent to the selected word line j, is disturbed by the word line coupling voltage (V.sub.cp). Then, by this V.sub.cp generated at the word line k, the unselected memory cell k having data `0` is disturbed by the memory cell disturbance voltage (V.sub.cd) in the half-V.sub.cc bit line precharge scheme. If the disturbed cell k, is selected for the next cycle, then V.sub.cp generated at the word line j and memory cell j is also disturbed by V.sub.cd, thereby increasing the noise/signal ratio dramatically. The combined amount of noise caused by both the word line and bit line coupling would be intolerable for proper DRAM operations, particularly for high-speed, low-power DRAMs.
An object of the present invention is to provide a twisting technique which can be applied to both BLs and WLs to reduce coupling noise without incurring other problems such as increased chip area and the need for special circuitry.